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In many communications environments it is desirable to “spread” the signal across as much of the allocated frequency spectrum as possible. This is usually done for one of three reasons:

 

• to enhance security of the communications channel (often in conjunction with channel hopping)
• to tolerate noisy channels
• to minimise inter-channel interference (by increasing the effective gain of the signal path)

This model is essentially a finite state machine (FSM) that generates an oversampling signal from the binary data stream in a digital communications system, for example, a wireless LAN. The FSM generates a codeword according to the gain required of the system, in this case a factor of 12 is needed. The codeword modifies the binary data stream in order to increase the effective data rate, for example:

1 -> 101101001010

0 -> 010010110101

There are a variety of solutions to implementing this increase in data rate. One solution is to use a shift register running at 12x the original data rate, but this requires a large number of registers. The most compact solution that we found was to implement a 12-state state machine. The key to minimizing the hardware is simply the ability to recognise patterns in the state vector register's output sequence (remember that patterns analysis was also used to minimize the hardware in the scaler Model).

A ‘both-edges' FSM implemented as two separate FSMs has the advantage of reducing the operating frequency of the design. The two FSMs must be coded as two separate processes for synthesis. In addition, the fsm_toggle process which is clocked from the output of the negative-edge clocked FSM must also be coded in a separate process for synthesis.

The spectrum spreader is implemented as a FSM to mimimize the amount of hardware. Once again, we find that hardware design skills plus a comprehensive knowledge of coding VHDL for synthesis are required to achieve the best design. Shown below is the RTL schedule or timing diagram (call it what you will) for the both_edges architecture.

You are welcome to use the source code we provide but you must keep the copyright notice with the code (see the Notices page for details).

-- Spectrum Spreader
-- +----------------------------+
-- | Copyright 1997-2008 DOULOS |
-- +----------------------------+

architecture both_edges of spectrum_spreader is

  signal state_pos : std_logic;
  signal state_neg : std_logic;
  signal state_toggle : std_logic;

begin

  SVR_pos : process (clock, reset)
  -- this flip-flop toggles when state_neg is 1 during state_toggle HIGH
  -- but then toggles on each clock when state_toggle is LOW
  begin
    if reset = '0' then
      state_pos <= '0';
    elsif RISING_EDGE(clock) then
      if state_toggle = '1' then
        if state_neg = '1' then
          state_pos <= not state_pos;
        end if;
      else -- state_toggle = '0'
        state_pos <= not state_pos;
      end if;
    end if;
  end process;

  SVR_neg : process (clock, reset)
  -- this is simply a toggle flip-flop with reset
  begin
    if reset = '0' then
      state_neg <= '0';
    elsif FALLING_EDGE(clock) then
      state_neg <= not state_neg;
    end if;
  end process;

  fsm_toggle : process (state_neg, reset)
  -- toggles on the +ve edge of state_neg when state_pos LOW
  begin
    if reset = '0' then
      state_toggle <= '0';
    elsif RISING_EDGE(state_neg) then
      if state_pos = '0' then
        state_toggle <= not state_toggle;
      end if;
    end if;
  end process;

  output: spread_data <= (state_pos xor state_neg) xor RF_data;

end both_edges;

To download the VHDL source code for this model, click here.

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