Clock Domain Crossing

Find a Training Course

Clock Domain Crossing

1 hour session (All Time Zones)
Presenter: Charles Gardiner

Doulos Certified Training Instructor

Asia and Europe

Time: 10-11am (GMT) 11-12pm (CET) 3.30-4.30pm (IST)

Americas

Time: 10-11am (PST) 11-12pm (MST) 12-1pm (CST) 1-2pm (EST)

Webinar Overview:

The primary goal in safely implementing any IC or FPGA project is to achieve a synchronous design. This implies that the relationship of all clocks and asynchronous resets to each other is defined in the synthesis constraints. Incorrect handling of clock-domain crossing (CDC) is probably the primary cause of sporadic errors, which are impossible to catch in a digital simulation and can cause a system to inexplicably fail in the field.

This webinar discusses situations in which CDC problems can occur and more importantly presents solutions for the most frequent scenarios.

Topics include:

What causes metastability
How to correctly implement CDC logic for simple signals, complex data and counters
How to use Synopsys Design Constraints (SDC) to ensure that static timing analysis (STA) produces reliable results in the context of multi-clock designs

The webinar will also feature a working example from Microchip® using PolarFire® FPGAs and SoCs and the Libero® SoC Design Suite.

Charles Gardiner - Doulos Certified Training Instructor - will be presenting this training webinar, which will consist of a one-hour session and will be interactive with Q&A participation from attendees.

Attendance is free of charge

If you have any queries, please contact webinars@doulos.com

More FREE online support resources with Doulos KnowHow

Doulos Knowhow includes

Technical information
Coding examples
Guidelines
Tips
Tutorials
Video guides
Downloads

Visit www.doulos.com/knowhow

Related training available from Doulos:

Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

Clock Domain Crossing

Find a Training Course