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Comprehensive VHDL is the industry standard 5-day training course teaching the application of VHDL for FPGA and ASIC design. Fully updated and restructured to reflect current best practice, engineers can attend either the individual modules, or the full 5-day course.
Workshops comprise approximately 50% of class time and are based around carefully designed exercises to reinforce and challenge the extent of learning.
Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported by this course include:
The course includes specific lab support for tool sets from the leading FPGA vendors including the vendor's native simulation and place-and-route tools.
The tool options available on a specific scheduled course may vary. Preferences can be selected in the booking process. Or please contact Doulos to discuss specific requirements.
Delegates must have attended Essential Digital Design Techniques or an equivalent course, or have a good working knowledge of digital hardware design. No previous knowledge of VHDL or a software language is required.
Delegates attending only the Advanced VHDL module must have some hardware design experience, and have completed the VHDL for Designers module or an equivalent course. We have found that delegates frequently overestimate their own capabilities. If in doubt, you will probably benefit from attending the full Comprehensive VHDL course.
Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:
If you would prefer a paperback version of your Doulos Golden Reference Guide, this can be purchased from the Doulos online shop.
The scope and application of VHDL • Design and tool flow • FPGAs • The VHDL world
The basic VHDL language constructs • VHDL source files and libraries • The compilation procedure • Synchronous design and timing constraints
Simulation • Synthesis • Place-and-Route • Device programming
Entities and Architectures • Std_logic • Signals and Ports • Concurrent assignments • Instantiation and Port Maps • The Context Clause
The Process statement • Sensitivity list versus Wait • Signal assignments and delta delays • Register transfers • Default assignment • Simple Testbenches
If statements • Conditional signal assignments and Equivalent process • Transparent latches • Case statements • Synthesis of combinational logic
VHDL types • Standard packages • Integer subtypes • Std_logic and std_logic_vector • Slices and concatenation • Integer and vector values
Arithmetic operator overloading • Arithmetic packages • Mixing integers and vectors • Resizing vectors • Resource sharing
RISING_EDGE • Asynchronous set or reset • Synchronous inputs and clock enables • Synthesisable process templates • Implying registers
Enumeration types • VHDL coding styles for FSMs • State encoding • Unreachable states and input hazards
Array types • Modelling memories • IP Generators • Instantiating generated components • Implementing ROMs
TEXTIO • READ and WRITE • Using TEXTIO for testbench stimulus and outputs • STD_LOGIC_TEXTIO
Variables • Loops • Std_logic and resolution • Array and integer subtypes • Aggregates
Hierarchical design flow • Library name mapping • Component declaration • Configuration • Hierarchical configurations • Compilation order
Array and type attributes • Port Maps • Generics and Generic Maps • Generate statement • Generics and generate
Subprograms • Procedures • Functions • Parameters and Parameter Association • Package declarations • Package bodies • Subprograms in packages • Subprogram overloading • Operator overloading • Qualified expressions • RTL Procedures
Assertions • Opening and closing files • Catching TEXTIO errors • Converting between VHDL types and strings • Checking simulation results • Initialising memories • Foreign bodies
Rationale for gate level simulation • VITAL tool flow • Reuse of RTL testbench at gate level • Comparison of RTL and gate level results • Behavioural modelling
|12 Jun 2023||Ankara, TR||Enquire|
|26 Jun 2023||Munich, DE||Enquire|
|24 Jul 2023||Ringwood, UK||Enquire|
|7 Aug 2023||Heesch, NL||Enquire|
|21 Aug 2023||Ankara, TR||Enquire|
|21 Aug 2023||Munich, DE||Enquire|
|18 Sep 2023||Ringwood, UK||Enquire|
|27 Nov 2023||Ringwood, UK||Enquire|
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