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Everything you wanted to know about VHDL configurations

1 hour session (All Time Zones)
Presenter: Matt Bridle

Doulos Certified Training Instructor

Asia and Europe

Time: 10-11am (GMT) 11am-12pm (CET) 3.30-4.30pm (IST)

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Americas

Time: 10-11am (PST) 11-12pm (MST) 12-1pm (CST) 1-2pm (EST)

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Webinar Overview:

VHDL configurations are a much maligned, much ignored part of the VHDL language. Consequently, many VHDL designers find them quite scary.

This webinar seeks to answer the questions you may not have had answered in the past; shedding light on the mystery of VHDL configurations and showing a practical example of how to apply them, using Synopsys VCS in the Doulos EDA Playground environment.

  • Topics include:
  • VHDL Entity and Architecture
  • Direct Instantiation
  • Component Declaration and Instantiation
  • VHDL Configuration Declaration
  • Default Binding Rules
  • Hierarchical and Nested Configurations
  • Other Capabilities
  • Compilation Order and Configurations

Doulos Certified Training Instructor, Matt Bridle, will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.

Matt Bridle

Matt Bridle - Doulos Certified Training Instructor - will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.

Attendance is free of charge

If you have any queries, please contact webinars@doulos.com

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