Here you can download the following paper:
- Event: SNUG UK, SNUG Germany and SNUG France, 2012
- Title: "A Beginner's Guide to Using SystemC TLM-2.0 IP with UVM"
- Author: David Long, John Aynsley and Doug Smith, Doulos
- Abstract: UVM 1.x includes support for the communication interfaces defined by the SystemC TLM-2.0 standard, although some implementation details differ. This enables integration of SystemC TLM-2.0 IP into a SystemVerilog UVM verification environment. The connection between SystemC and SystemVerilog currently requires a tool-specific language interface such as Synopsys TLI, since it is not yet implemented as part of UVM. This paper begins with a brief overview of TLM-2.0 aimed at novice users. It then discusses the steps required to add a SystemC TLM-2.0 model into a SystemVerilog UVM environment and simulate it with VCS. At each step, issues that users will face are explored and suggestions made for practical fixes, showing the relevant pieces of code. Finally, the paper gives a summary of areas where the UVM implementation of TLM-2.0 differs from the SystemC standard and proposes workarounds to ensure correct communication between the SystemVerilog and SystemC domains.
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