What is Easier UVM?
Easier UVM consists of the Easier UVM Coding Guidelines and the Easier UVM Code Generator. Easier UVM was created by Doulos as a service to the UVM community and is freely available from this website. You may use the Easier UVM Coding Guidelines as they are, merge them into your own company-specific UVM coding guidelines, or merely borrow some of the ideas. The Easier UVM Code Generator is a Perl script provided under the Apache 2.0 license (see the FAQ). You can also run the code generator from the EDA Playground website (see this video). There is extensive documentation and video tutorials on Easier UVM itself, and a series of video tutorials that teach UVM by taking advantage of Easier UVM and EDA Playground - see the links at the bottom of this and every Easier UVM webpage.vm/easier_uvm_guidelines">Coding Guidelines and a Code Generator.
The Easier UVM Coding Guidelines and Code Generator
You can get the Easier UVM Coding Guidelines and Code Generator here
Resources, training, events and webinars
Following the success of Easier UVM events and webinars over the past year, Doulos will continue to develop resources to assist engineers in getting to grips with SystemVerilog and UVM.
Please bookmark this web page: more resources, training opportunities, events and webinars will be posted here regularly.
On-line training webinars:
- NEW: Easier UVM: Helping FPGA Designers Get Started with UVM - Find out more »
In this webinar we introduce the Easier UVM Coding Guidelines and Code Generator from Doulos, and show how Easier UVM can help you start to gain confidence with UVM by generating your own examples that run out-of-the-box.
- Easier UVM: First Steps with UVM: Writing Tests - Find out more »
Whether you are evaluating UVM or starting to write your own code, this webinar will show you how to take the first steps in writing tests.
It includes how to write and start sequences, how to customize the behavior of existing sequences from a test, and how to abstract the test from the details of the design-under-test using the UVM Register Layer.
- UVM: Now or Never - Find out more »
This webinar highlights the reasons why you should (or in a few cases should not) be adopting UVM right now, and explains how using SystemVerilog with UVM to create your test benches differs from using Verilog or VHDL.
It explores some of the practicalities of migrating to UVM from other methodologies, discusses using UVM alongside C/SystemC reference models, and introduces register modeling using the UVM register layer.
- Easier UVM: Introduction - Find out more »
Still writing test benches in Verilog or VHDL? Need a better approach to improve your functional verification? Need help with the transition from Verilog or VHDL to SystemVerilog? Looking for guidance on learning and using UVM, the Universal Verification Methodology for SystemVerilog? This webinar will help you tackle these questions.
Let me know when this webinar will run »
- Easier UVM: First Steps with UVM - Find out more »
This webinar will get you started with UVM by walking through some very simple examples of working UVM code, explaining what is happening and highlighting both best practice and common pitfalls.
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- The Finer Points of UVM Sequences »
This webinar is of interest to UVM newcomers who are trying to figure out how sequences work, and also to more experienced UVM programmers who want to understand the finer points.
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- Easier UVM: Register Layer - Find out more »
This webinar covers the purpose of the register layer and explains the user interface, as well as how to construct a register model, integrate it into a verification environment, use it in tests and take advantage of the built-in register tests.
Let me know when this webinar will run »
UVM training and resources available NOW from Doulos:
