Full Training Programs
Free Technical Resources
It is often reported that a large number of ASIC designs meet their specifications first time, but fail to work when plugged into a system. VHDL allows this issue to be addressed in two ways: A VHDL specification can be executed in order to achieve a high level of confidence in its correctness before commencing design, and may simulate one to two orders of magnitude faster than a gate level description. A VHDL specification for a part can form the basis for a simulation model to verify the operation of the part in the wider system context (eg. printed circuit board simulation). This depends on how accurately the specification handles aspects such as timing and initialization.
Behavioural simulation can reduce design time by allowing design problems to be detected early on, avoiding the need to rework designs at gate level. Behavioural simulation also permits design optimization by exploring alternative architectures, resulting in better designs.
VHDL descriptions of hardware design and test benches are portable between design tools, and portable between design centres and project partners. You can safely invest in VHDL modelling effort and training, knowing that you will not be tied in to a single tool vendor, but will be free to preserve your investment across tools and platforms. Also, the design automation tool vendors are themselves making a large investment in VHDL, ensuring a continuing supply of state-of-the-art VHDL tools.
VHDL permits technology independent design through support for top down design and logic synthesis. To move a design to a new technology you need not start from scratch or reverse-engineer a specification - instead you go back up the design tree to a behavioural VHDL description, then implement that in the new technology knowing that the correct functionality will be preserved.
Your e-mail comments are welcome - send email