In implementing arithmetic circuits be very careful how you write the VHDL code, particularly for designs that are sensitive to area.
For example, consider a clock-enabled counter:
process (clock)
begin
if RISING_EDGE(clock) then
if enable then
count <= count + 1;
end if;
end if;
end process
This realises a standard register with incrementer in the feedback loop implementation. But it also creates a multiplexer in the data path to implement the enable logic. Could be quite a bit more area, couldn't it? The use of the if statement for the enable is the source of the problem. How about a solution or two?
One approach is to directly gate the clock:
enabled_clock <= clock and enable;
process (enabled_clock)
begin
if RISING_EDGE(enabled_clock) then
count <= count + 1;
end if;
end process;
which might yield interesting comments at design review time!
However, is that clock gating even necessary?
By re-writing as:
process (clock)
begin
if RISING_EDGE(clock) then
count <= count + enable;
end if;
end process;
The carry-in to the incrementer ought to be used by the enable (or perhaps the ‘1' of the incrementer will be driven by enable). The disadvantage to this approach is that for cases where the enable is on the critical path, the carry-in connection could pose timing problems.
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