Let's look at how an 8-bit by 8-bit multiplication can be implemented in an FPGA device. The optimal implementation is influenced by many aspects of the design process, including the coding style, the synthesis tool's features and the target technology. Many times, however, the optimal solution is most heavily influenced by the architecture chosen by the designer. There are a host of architectures to choose from in implementing a multiplier:
- shift and add
- Wallace Tree
to name just a few.
In this tip, we're going to look at the use of LUT-based multipliers implemented in a typical FPGA device. Advantage is taken of the RAM-like structures implemented in the FPGA devices. For example, in Altera FLEX10K devices, these structures are called embedded array blocks or EABs.
An EAB can be configured as a 256 x 8-bit logic function, allowing for the implementation of a 4-bit x 4-bit multiplier. The two 4-bit operands consume the 8-bit Address input to the EAB, the 8-bit Data Out output provides the product of the two inputs. For an 8-bit x 8-bit multiplier, four EABs can be arranged to accommodate the appropriate nibbles of the two inputs together for each EAB whilst the partial product outputs from each EAB can be added together using LEs.
A comparison of the EAB approach versus the LE-only approach yields the following results:
|TECHNIQUE||EAB count||LE count|
|EAB + LE||4||29|
An EAB is equivalent to 8 LEs, so you do achieve a small reduction in resource usage of the FLEX10K device!
Implementing the multiplier using the EAB requires the feature to be available in the synthesis tool you are using - perhaps the ability to infer EABs for logic functions in your HDL code along with a tool-specific directive. Alternatively, you may have to instantiate an LPM component in the HDL code if the synthesis tool you are using can map LPMs to EABs.
These device-specific considerations are taught in some detail in our Altera and Xilinx courses and our Comprehensive VHDL and Verilog training courses.
Bye for now...
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