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Ports can represent busses or vectors as well as single bits. In the example above, the port SEL is a 2-bit bus, with msb numbered 1 and lsb numbered 0. The type of the port is STD_LOGIC_VECTOR, which is also defined in package STD_LOGIC_1164 on library IEEE. Objects of type STD_LOGIC_VECTOR are simply an array of STD_LOGIC objects.
library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUX4 is port (SEL : in STD_LOGIC_VECTOR(1 downto 0); A, B, C, D: in STD_LOGIC; F : out STD_LOGIC); end MUX4;
In the previous example, an array type was used to allow the description in VHDL of a vectored port. Array types can be used for internal signals as well as ports. This can be seen in the MUX4 testbench code below:
entity TEST_MUX4 is ... architecture BENCH of TEST_MUX4 is ... signal SEL: STD_LOGIC_VECTOR(1 downto 0); ... begin SEL <= "00", "01" after 30 NS, "10" after 60 NS, "11" after 90 NS, "XX" after 120 NS, "00" after 130 NS; ... M: MUX4 port map (SEL, A, B, C, D, F); end BENCH;
The stimulus for the SEL signal is shown as a waveform, made up of individual waveform elements. A waveform element consists of an expression followed by a time specification for when the signal is driven by the value of the expression. In this particular case, the expression is a STD_LOGIC_VECTOR literal. STD_LOGIC_VECTOR values can be written as bit string literals. For example both bits are set to '0 at time 0, while at time 30 ns, SEL (1) is set to '0' and SEL (0) is set to '1'.
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