Introduction to AMD Zynq Utrascale+ MPSoC (Self-Paced)
Overview • Processing System • CCI General Configuration • AXI ACE and DVM extensions • SoC Implementation Choices • Development Tools
Introduction to the 32 bit Arm Architecture (Self-Paced)
Architecture versions • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions • The Future
ArmV7-A/R A32 Instruction Set Overview (Self-Paced)
Load/Store • Data Processing • Flow Control • Misc • DSP
AArch32 Exception Handling (Self-Paced)
Introduction • Interrupts • Abort Handlers • SVC Handlers • Undef • Handlers • Reset Handlers
Software Engineer's Guide to the Cortex-R5 (Self-Paced)
Introduction • Twin CPU support • L1 memory system • Error detection • Misc
Using the MPU (Self-Paced)
Memory Management Introduction • Access Permissions and Types • Memory Protection Unit (MPU) • Optimizations & Issues
Architecture Overview
Privilege levels • AArch64 registers • A64 Instruction Set • AArch64 Exception Model • AArch64 Memory Model
Software Engineer's Cortex®-A53
Core pipelines • Configuration options • Branch prediction • Cache overview • Data cache coherency • Memory management • Micro-architectural features • Interrupts and bus interfaces • Debug and timers • Big-little
A64 ISA Overview
Registers • Loads and stores • Data processing and control flow • Scalar floating-point and SIMD
Synchronization
Synchronization in Armv8-A • Local and Global Exclusive Monitors
AArch64 Exception Model
The AArch64 exception model • Interrupts • Synchronous exceptions • SError • exceptions • Exceptions in EL2 and EL3
Booting
Booting an Armv8-A processor in AArch64 • Booting multi-core and multi-processor systems • Real-world booting
Caches and Branch Prediction
General Cache Information • Cache Attributes • Cache Maintenance Operations • Cache Discovery
Memory Management
Memory Management theory • Stage 1 Translations at EL1/0 • Translations at EL2 / EL3 • TLB maintenance
Memory Model
Types • Attributes • Alignment and endianness • Tagged pointers
Barriers
Data barriers • Instruction barriers
Armv8-A OS Support Features
Context Switching • Modifying Translation Tables • Privilege Escalation Protections • Timers
Secure Environments
Why do we need a Secure environment? • Software stack • System architecture
Cache Coherency
Introduction to coherency • Coherency details - multi-core processors • Coherency details - multi-processor systems
Virtualization
What is virtualization? • Arm virtualization support • Memory management • Exception handling
Cortex-A Power Management
Arm core power modes • Power control • Arm multi-core processor power modes • Power state coordination
Embedded Software Development
Semihosting / retargeting • Mixing C/C++ and assembly • Application Startup • Tailoring image memory map to your target • Accessing memory mapped peripherals • Additional considerations
GNU Compiler Hints and Tips
Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data Issues
GNU Linker Hints and Tips
Linking Basics • System and User Libraries • Linker Script • Veneer and Interworking • Linker Optimizations and Diagnostics • GNU Embedded Development Libraries
Armv8-A Debug
Introduction to Debug • Types of Debug • Debug Facilities • External Debug • Self-hosted Debug • CoreSight • Debug Features • Trace
NEON Benchmarking and Performance Analysis
Introduction • Performance Monitoring Hardware: PMU • Cycle Accurate Trace: Trace • Macrocells • Streamline Performance Analysis
Appendix
Software Engineer's Guide to System Fabric
Interrupt Controller • System MMU • TrustZone Address Space Controller • Generic Timer
