Arm Cortex-A53/R5 for Zynq UltraScale+ MPSoC

• Engineers who wish to become skilled in the use of an hybrid Arm Cortex-A53/R5 based System On Chip from a software and verification perspective

• Engineers who are required to provide a software solution to bring a bare metal Arm Cortex-A53/R5 MPCore system to life

• The hardware structure of a Zynq UltraScale+ device
• The details of an Arm Cortex-A53 processor core
• The details of an Arm Cortex-R5 processor core
• The details of the MPCore logic
• Memory management for Arm v8-A based devices
• Assembly programming for the T32/A32/A64 instruction sets
• Writing efficient C code for the Cortex-A53
• Bringing up an Arm Cortex-A53 bare metal system
• Exception handling

Delegates should have some knowledge of embedded systems and a basic understanding of embedded programming in C and assembler. Knowledge of earlier Arm architectures is an advantage but not required.

C programming for Embedded Systems training is also available from Doulos.

A carefully crafted combination of content from Arm, AMD and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.

Due to the exhaustive list of topics covered in this class, the material is provided as a combination of self-paced content and live in-person sessions. For on-site classes, it is possible to cover the self-paced content in a in-person sessions by adding an extra day of training delivery to the existing four.

Please speak to a member of your local Doulos sales team to discuss your custom requirement.

The self-paced content should be viewed as pre-requisite knowledge that the student will have to acquire prior to the instructor led training. The modules are fully indexed videos, browsable slide by slide and accessible both on a computer or a portable device. No software installation is required for accessing the video content.

The self-paced modules are accompanied by numerous hands-on exercises found inside the same virtual machine provided for the main instructor led training class.

Introduction to AMD Zynq Utrascale+ MPSoC (Self-Paced)

Overview • Processing System • CCI General Configuration • AXI ACE and DVM extensions • SoC Implementation Choices • Development Tools

Introduction to the 32 bit Arm Architecture (Self-Paced)

Architecture versions • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions • The Future

ArmV7-A/R A32 Instruction Set Overview (Self-Paced)

Load/Store • Data Processing • Flow Control • Misc • DSP

AArch32 Exception Handling (Self-Paced)

Introduction • Interrupts • Abort Handlers • SVC Handlers • Undef • Handlers • Reset Handlers

Software Engineer's Guide to the Cortex-R5 (Self-Paced)

Introduction • Twin CPU support • L1 memory system • Error detection • Misc

Using the MPU (Self-Paced)

Memory Management Introduction • Access Permissions and Types • Memory Protection Unit (MPU) • Optimizations & Issues

Architecture Overview

Privilege levels • AArch64 registers • A64 Instruction Set • AArch64 Exception Model • AArch64 Memory Model

Software Engineer's CortexA®-A53

Core pipelines • Configuration options • Branch prediction • Cache overview • Data cache coherency • Memory management • Micro-architectural features • Interrupts and bus interfaces • Debug and timers • Big-little

A64 ISA Overview

Registers • Loads and stores • Data processing and control flow • Scalar floating-point and SIMD

Synchronization

Synchronization in Armv8-A • Local and Global Exclusive Monitors

AArch64 Exception Model

The AArch64 exception model • Interrupts • Synchronous exceptions • SError • exceptions • Exceptions in EL2 and EL3

Booting

Booting an Armv8-A processor in AArch64 • Booting multi-core and multi-processor systems • Real-world booting

Caches and Branch Prediction

General Cache Information • Cache Attributes • Cache Maintenance Operations • Cache Discovery

Memory Management

Memory Management theory • Stage 1 Translations at EL1/0 • Translations at EL2 / EL3 • TLB maintenance

Memory Model

Types • Attributes • Alignment and endianness • Tagged pointers

Barriers

Data barriers • Instruction barriers

Armv8-A OS Support Features

Context Switching • Modifying Translation Tables • Privilege Escalation Protections • Timers

Secure Environments

Why do we need a Secure environment? • Software stack • System architecture

Cache Coherency

Introduction to coherency • Coherency details - multi-core processors • Coherency details - multi-processor systems

Virtualization

What is virtualization? • Arm virtualization support • Memory management • Exception handling

Cortex-A Power Management

Arm core power modes • Power control • Arm multi-core processor power modes • Power state coordination

Embedded Software Development

Semihosting / retargeting • Mixing C/C++ and assembly • Application Startup • Tailoring image memory map to your target • Accessing memory mapped peripherals • Additional considerations

GNU Compiler Hints and Tips

Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data Issues

GNU Linker Hints and Tips

Linking Basics • System and User Libraries • Linker Script • Veneer and Interworking • Linker Optimizations and Diagnostics • GNU Embedded Development Libraries

Armv8-A Debug

Introduction to Debug • Types of Debug • Debug Facilities • External Debug • Self-hosted Debug • CoreSight • Debug Features • Trace

NEON Benchmarking and Performance Analysis

Introduction • Performance Monitoring Hardware: PMU • Cycle Accurate Trace: Trace • Macrocells • Streamline Performance Analysis

 

Appendix

 

Software Engineer's Guide to System Fabric

Interrupt Controller • System MMU • TrustZone Address Space Controller • Generic Timer

The learning is reinforced with unique Lab Exercises using an Armv8-A 64 bit instruction set simulator and covering assembly programming, exception handling and setting up the caches and MMU.

• Lab exercises for assembly programming cover the concepts of data processing, flow control, and rely on the GNU development tool-set
• Exception handling lab exercises look at setting up various exception levels vector table and execution modes as well as executing hypervisor and secure calls
• The Memory management lab takes you though the steps involved in implementing a typical system memory configuration using the MMU
• The performance monitoring unit lab takes you through the steps required to configure and enable performance monitoring inside your processor

For teams designing applications that utilise the real-time R5 processor within the UltraScale+ MPSoC, a custom onsite training program can be delivered incorporating additional content from the Arm Cortex-R5 Software Design course.

• Custom onsite courses are available worldwide.
• The extended agenda and training timetable increase the program to a minimum of 5 days duration
• Please speak to a Doulos technical staff member about your application needs via your local Doulos sales office