Arm Cortex-M3/M4 SoC Design

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Arm Cortex-M3/M4 SoC Design

Standard Level - 3 days

Arm® Cortex®-M3/M4 SoC Design is a 3-day class for engineers designing hardware based around the Arm Cortex-M3/M4 core. It includes an introduction to the Arm product range and supporting IP, programmer's model, instruction set architecture, AMBA on-chip bus architecture and Cortex-M3/M4 debug architecture. The class includes a number of worked examples developed by Arm to reinforce the lecture material.

Who should attend?

Hardware design engineers who need to understand the issues involved when designing SoC's around the Arm Cortex-M3/M4 core.

Pre-requisites

Some knowledge of embedded systems and familiarity with digital logic and hardware/ASIC design issues. A basic awareness of Arm is useful but not essential.

Training materials

This class uses training materials developed by Arm®

Content

Day 1

Cortex-M3/M4 Overview

An overview of the Cortex-M3 and Cortex-M4 processor cores that discusses the pipeline, memory map and other key features.

Cortex-M3/M4 Core

Detailing the processor pipeline and instruction execution.

Armv7-M Exception Handling

Introduces the exception handling model for Architecture v7-M. Explains how to write software handlers and manage interrupts.

Assembler Programming

Outlines the main features of the Thumb instruction set. Provides a primer for those needing to interpret compiler output or write low level code.

Cortex-M4 Details

Showing the differences between Cortex-M3 and Cortex-M4. Introducing DSP and SIMD instructions, Floating Point Unit and extended exception stack frame.

Day 2

AMBA AHB-Lite

Explains the AMBA 3 AHB-Lite Bus protocol.

AMBA APB

Explains the AMBA APB Bus protocol.

Cortex-M3/M4 System Interfaces

Detailed discussion of the memory system bus interfaces at the processor and integration levels.

Cortex-M3/M4 Clocks, Reset Power

Explains the reset and clocking requirements and operation of sleep modes. Introduces the Wake-up Interrupt Controller.

Cortex-M3/M4 Memory Protection

Introduces the Memory Protection Unit. Explains memory types and attributes, and how to configure memory protection regions.

SysTick Timer

Introduces the built-in System Timer function and explains the calibration function.

Day 3

Cortex-M3/M4 Debug and Trace

Introduces CoreSight and the DAP components and ROM Table. Overview of Debug and Trace capabilities and standard debug connectors.

Cortex-M3/M4 Debug

Detailed view of debug capabilities, DAP components, and Flash Patch & Breakpoint Unit.

Cortex-M3/M4 Trace

Explanation of instruction trace methodology. Detailed view of instrumentation trace and data watchpoint and trace units and trace port. Discussion of trace clocking.

Cortex-M3/M4 Examples

Brief overview of Cortex-M3 example system and Cortex-M4 Integration Kit. Introduction to ‘tarmac’ and to multi-processor integration.

Cortex-M3/M4 Implementation

Details of RTL configuration. Overview of design flow steps and introduction to Reference Methodologies.

Cortex-M system Design Kit

Overview of CMSDK components and example systems.

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Arm Cortex-M3/M4 SoC Design

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