Day 1
Introduction to the Arm Architecture
Architecture versions • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions
Arm Tools Overview
Arm DS-5 • Tool Licensing • GNU and ABI • Debug Interfaces
Assembler Programming for Arm Processors
Load/Store Instructions • Data Processing Instructions • Flow Control • Miscellaneous • DSP
Exception Handling
Exceptions overview • Interrupts sources and priorities • Abort Handlers • SVC Handlers • Undef Handlers • Reset Handlers
Day 2
Arm Caches and TCMs
Cache basics • Caches on Arm processors • Tightly Coupled Memory (TCM) • Optimization consideration
Using the MPU
Memory Management Introduction • Access Permissions and Types • Memory Protection Unit (MPU) • Optimizations & Issues
C/C++ Compiler Hints & Tips
Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data issues
Linker & Libraries Hints & Tips
Linking Basics • System and User Libraries • Veneers and Interworking • Linker Optimizations and Diagnostics • Arm Supplied Libraries
Debug and Profiling
Invasive Debug • Non-Invasive Debug • PMU • Trace
Day 3
Software Engineers' Guide to the Cortex-R5
Introduction • Twin CPU support • L1 memory system • Error detection • Instruction set changes
Further Compiler/Linker Hints & Tips
Mixing C/C++ and Assembler • Stack Issues • VFP/NEON • Advanced Building Facilities Embedded Software Development
Embedded Software Development
An "Out-of-the-box" build • Tailoring the C library to your target • Tailoring image memory map to your target • Reset and Initialization • Further memory map considerations • Building and debugging your image
Power Management for Cortex-A/R Cores
Processor Power Consumption • Power Modes • NEON and MPCore
Debug and Trace
Debug Logic Overview • Debug Logic Features • Tools use of Debug Logic • Trace Logic Overview • Debug vs. Trace • System Level Debug Infrastructure • CoreSight Introduction CoreSight Debug • CoreSight Trace
