Introduction to the Arm Architecture
Architecture versions • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions • The Future
Software's Guide to Cortex-R8
Cortex-R8 • MPCore • Overview • Operational modes • Level 1 Memory system • Level 2 Interface • Multiprocessing features
ArmV7-A/R ISA Overview
Load/Store • Data Processing • Flow Control • Misc • DSP
Exception Handling
Introduction • Interrupts • Abort Handlers • SVC Handlers • Undef • Handlers • Reset Handlers
Caches and TCMs
Cache basics • Caches on Arm processors • Tightly Coupled Memory (TCM) • Optimization considerations
Synchronization
Introduction to atomicity • Load exclusive and store exclusive instructions • Code examples • Multi-core, coherency • Exclusive reservation granule
Using the Memory Protection Unit
Types & Attributes • Memory Protection Unit (MPU)
Understanding Barriers
Data barriers • Instruction barriers
Power Management for Cortex-A/R Cores
Processor Power Consumption • Power Modes • NEON and MPCore
Embedded Software Development
Semihosting / retargeting • Mixing C/C++ and assembly • Application Startup • Tailoring image memory map to your target • Accessing memory mapped peripherals • Additional considerations
GICv1 & GICv2 Programming
Distributor and CPU Interfaces • How to enable and configure interrupts • How to handle interrupts • How to send software interrupts • Security Extensions
Debug
Invasive Debug • Non-Invasive Debug • PMU • Trace
GNU Compiler Hints and Tips
Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data Issues
GNU Linker Hints and Tips
Linking Basics • System and User Libraries • Linker Script • Veneer and Interworking • Linker Optimizations and Diagnostics • GNU Embedded Development Libraries
