Duration: 5 sessions (7 hours per session)
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE. Please note for this course, daily sessions are up to 7 hours including breaks.
It covers the same scope and content as a scheduled in-person class and delivers comparable learning outcomes.
This course is designed for engineers developing software for platforms based around Arm® Cortex®-M Series processors with v6-M and v7-M architecture. The course includes an introduction to the Arm product range and supporting IP, the processor core, programmers' model, instruction set and debug architecture. It includes a number of worked examples and hands-on CMSIS compliant exercises to reinforce the training material. It also includes content on the very latest M Series cores.
Hands-on Labs
The learning is reinforced with unique Lab exercises which are run inside a self contained virtual machine environment. This allows the student to experience a real-life and project-ready development environment without the complexity of installing complex software prior to the class. This virtual machine is for the student to keep after the training class, allowing you to further experiment with embedded software development once the class has come to completion.
The format of Live ONLINE training from Doulos is focused on delivery of a single 5 to 6 hours session per day. This includes live tuition and class interaction with the Doulos subject matter expert during the full scope of each session.
Software engineers writing C/C++ based applications for platforms using the Arm Cortex-M processor cores: M0, M0+, M3, M4 and M7.
For training on Armv8-M based cores visit: Cortex-M23 and Cortex-M33.
For delegates interested in the security features of the Cortex-M23/M33/M35 & M55, the Arm TrustZone-M for Cortex-M23/M33 ONLINE is ideal follow-on training.
- Some knowledge of embedded systems
- Basic awareness of Arm is useful but not essential
- Experience of C or assembly programming is not required but would be beneficial
This class is based on source training material developed by Arm themselves, augmented with supplemental content and labs developed by Doulos. Doulos is a global Arm Approved Training Center.
The majority of the course content and sessions are relevant and of value for engineers developing products using platforms based on the current Cortex-M Series family (with Armv6-M and v7-M architecture). In public class delivery contexts, the specific agenda followed may vary from that indicated below dependent on the focus and interests of the course participants attending that event. Upon registration, course participants will be asked to indicate which specific M Series core they are focusing on, which will steer the class agenda to some degree.
Note the course includes a valuable comparison of capabilities and application variance between different members of the M Series family which will be of benefit to evaluators as well as those preparing for project.
For private team-based training for software developers, the course can be focused entirely on a specific M Series core. The course descriptions for these courses can be found below:
For private team based training for system designers and integrators, there are also course options available:
Session 1
- Introduction to Arm
Arm as a company • Processor portfolio • Supported architectures • Processor profiles
- Cortex-M Overview
Block diagram • Architectural features • Instruction set • Programmer's model • Memory map • Memory interfaces • Caches • Exception handing • Memory protection • Power management • Implementation options
- Cortex-M Programmers’ Model
Data types • Core registers • Modes, privileges and stack • Exceptions • Instruction set overview
- Assembly Programming
Data processing instructions • Load/Store instructions • Flow control • Miscellaneous instructions
Session 2
- Synchronization
Introduction to synchronization and semaphores • Exclusive accesses • Bit-banding
- Memory Model
Memory address space • Memory types and attributes • Alignment and endianness • Barriers
Data memory barrier • Data synchronization barrier • Instruction synchronization barrier • Barrier applications examples
- Memory Protection
Memory protection overview • Regions overview • Regions overlapping • Setting up the MPU
Session 3
- Embedded Software Development
Default compilation behavior • System startup • Tailoring the image memory map to a device • Post startup initialization • Tailoring the C library to a device • Building and debugging an image
- Compiler Hints & Tips
Basic Compilation • Compiler optimisations • Coding considerations • Mixing C/C++ and assembly • Local and global data issues
- Linker Hints and Tips
Linking basics • System and user libraries • Linker script • Veneer and interworking • Linker optimizations and diagnostics • GNU embedded development libraries
Session 4
- Exception Handling
Exception Model • Interrupts • Writing the vector table and interrupt handlers • Internal exceptions and RTOS support • Fault exception
- CMSIS Overview
CMSIS-Core • CMSIS-DSP • CMSIS-RTOS • CMSIS-SVD • CMSIS-DAP
Session 5
- Armv7-M Extensions
DSP • Folating Point
- Debug
Coresight and debug access port DAP • Debug event and reset • Flash patch and breakpoint unit (FPB) • Data watch point and trace unit (DWT) • Instrumentation trace macrocell (ITM) • Embedded trace macrocell (ETM) • Trace port interface unit (TPIU) • Implementation details
- Cortex-M7 L1 Sub-Systems
Caches • Tightly coupled memory (TCM) • System consideration
Our hands-on exercises are provided as a self-contained virtual machine that can easily be taken away by the students by the end of the class. Our virtual machine works on most operating systems and features a full pre-configured embedded development environment based in industry de-facto standards such as GNU tools and Eclipse. The laboratories work both on pre-installed instruction set simulators and the supplied microcontroller development boards.
The exercises cover a large spectrum of topics:
- assembly programming,
- data transfers,
- data processing,
- flow control,
- digital signal processing,
- exception handling with the implementation priority schemes and pre-emption
- mixing C and assembly to provide a semi-hosted solution.
STM32L552 Evaluation Board
