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This course is available Live Online worldwide: View the Live Online full course description »
In-person training schedule under review for 2022. Please contact us to discuss your requirements for in-person individual and team training.
Signal Integrity with Hands-On Simulation is a 3-day training course in practical signal integrity for board level design and layout engineers. The course alternates between teaching the essential theory and how to use simulations as part of day-to-day design work in an efficient way using industry standard IBIS simulators etc. Lots of practical examples and tips are given.
The course gives engineers confidence to handle signal and power integrity while designing board-level digital circuits. The emphasis is on understanding how the theory works for common real-world circuits with multiple digital parts on multilayer PCBs. Delegates learn to use simulations to find the requirements for layout that will work reliably and how to apply that in the design process.
The course is not focused on how to use a specific vendor’s toolset but rather how to get useful results using the tools available. The lab exercises are carefully designed to reinforce the theory and put it in a ready-to-use practical form without spending too much time on the specifics of the chosen tool.
Lab exercises comprise approximately 50% of class time.
Delegates must have a good working knowledge of digital hardware design. No previous knowledge of signal integrity or simulation tools is required. No advanced math is required.
The course fees include:
There is no requirement for the text book or any of the other books recommended, but they provide a good supplement for further reading and deeper understanding after the course.
Why signal integrity matters • Noise margin and noise sources • Reasons for board spins
Ideal transmission lines • Lossy transmission lines • Terminology • Calculating impedance • Dialectric constant of prepreg and laminates • Measuring impedance • Why 50 ohms?
Formulas • Recognizing low vs high source impedance • What is reflection and what is ringing?
Unterminated transmission lines • Parallel, series and RC termination • Why terminate? • When to terminate • Power consumption of termination
Multi-node nets •: Where to terminate • One vs. multiple drivers • One vs. multiple loads • Handling of connectors
Understanding the models • Process corner simulation • When IBIS simulation is not possible
Termination stubs • Understanding the quarter wavelength stub
PCI bus • SSTL termination • DDR1, DDR2, DDR3, DDR4 schemes • LVDS bus • Typical address and data bus simulation
Near-end vs. far-end crosstalk • Capacitive vs. inductive coupling • Critical length • Reducing crosstalk • Broadside vs. side-by-side • Guard traces • Reference plane
Principle for differential signalling • Advantages and disadvantages • Cable vs. on the board • Immune to common mode coupling? • Does differential routing make sense?
Power distribution model • Voltage ripple requirements • Noise margin considerations
Capacitor types • Ceramics • RLC models • Multi-terminal capacitors • Bulk capacitors • Land patterns • Effective inductance • Placement around vs. on the back side of a board • Interplane capacitance • Myths about bypass
Concept for finding the right amount of bypass • Spreadsheet simulation • PDN tool • Frequency range • Package model • On-package and on-die capacitance • Via inductance • Defining plane requirements
Test methods • Required equipment • Understanding the test setup and results • Preparing for doing the tests in your lab
Defining vcc bounce, ground bounce and SSN • Measuring ground bounce • Package lead inductance • Simple paper estimation • Finding peak I/O current • Simulating SSN with an IBIS simulator
Understanding noise sources on the board • Reflections • Crosstalk • SSN • Power supply variations • Ground offsets • Trace voltage drops and losses • Terminator noise • Skin effect • Dialectric loss • PCI Express example • Vtt example
Design flow • Building a design rule set • Efficient pre and post layout review technique
Skew and jitter • Loss impact on multi gigabit differential signalling • Pre/de-emphasis and receiver equalization
Understanding PCB materials • Copper • Prepreg and laminates • Selecting surface finish
Defining the PCB stack-up • Building a design rule set • Efficient pre and post layout review technique
Specifying the PCB stack-up • Materials • Patents • Test features for layer order • Test traces • Test points and probes for high-speed
Via types • Non-functional pads • Capacitance and inductance • Is the via a stub? • Via models • Understanding CAF • Backdrilling
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