1 hour session (All Time Zones)
The primary goal in safely implementing any IC or FPGA project is to achieve a synchronous design. This implies that the relationship of all clocks and asynchronous resets to each other is defined in the synthesis constraints. Incorrect handling of clock-domain crossing (CDC) is probably the primary cause of sporadic errors, which are impossible to catch in a digital simulation and can cause a system to inexplicably fail in the field.
This webinar discusses situations in which CDC problems can occur and more importantly presents solutions for the most frequent scenarios.
Attendance is free of charge
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