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Doulos Technotes contain in-depth information about a particular aspect of technology; in this case, FPGA technology. Our experts distil knowledge and experience and put it into an easy-to-read form, saving you time.
If you are new to HDLs, you'll want to look at our training for FPGA users Comprehensive VHDL.
If you are a more advanced user, our Expert VHDL training class offers expert training for FPGA users.
"HDL Synthesis Inference of FPGA Memories"
Jonathan Bromley, Doulos
This Doulos FPGA Technote gathers into one convenient document all the information you need about how to create memory blocks in FPGAs using VHDL or Verilog.
By using VHDL or Verilog HDL to describe synthesizable memory blocks you can make your code easier to read, faster to simulate, and much more portable across tools and devices. Despite these benefits, memory inference is not a "silver bullet" and it's important to understand clearly how your RTL coding choices affect the FPGA hardware implementation. Our aim in creating this Technote has been to provide you with the information you need in a convenient, vendor-independent and accessible form.
None of the information in this document is new. It is all available in the documentation supplied by FPGA and synthesis tool vendors, and of course you can easily try out various HDL coding styles for yourself. However, in this Technote you will find it collected together for easy reference regardless of which FPGA vendor, HDL or synthesis tool you choose. The code examples provide templates for your own development, and have been shown to work across a wide variety of synthesis tools and FPGA families.
FPGA Technote Contents include:
FPGA memory architecture and applications
Background
- Kinds of embedded memory blocks
- Inference or instantiation?
- Challenges for successful memory inference in synthesis
- Impact of memory size on synthesis results
- Upsizing and downsizing FIFOs
Portable coding styles for memory synthesis
Single-port memory architectures
- RAM with asynchronous read operation
- Synchronous RAM, one read-write port
Dual-port memory architectures
- Synchronous RAM with two ports sharing a common clock
- Synchronous RAM with two ports having independent clocks
The Designs
The HDL code
- Single port RAM with asynchronous read
- Design CWAR: synchronous write, asynchronous read
- Single port fully synchronous RAM
- Design CWR: single port, write-first
- Design CRW: single port, read-first
- Design CWnR: single port, no change on write
- Dual port synchronous RAM with common clock
- Design CWR_CWR: write-first on both ports
- Design CRW_CRW: read-first on both ports
- Design CWnR_CWnR: no-change on both ports
- Design CW_CR: one write-only port, one read-only port (FIFO)
- Dual port synchronous RAM with independent clocks
- Design C0WR_C1WR: write-first on both ports
- Design C0RW_C1RW: read-first on both ports
- Design C0WnR_C1WnR: no-change on both ports
- Design C0W_C1R: one write-only port, one read-only port (FIFO)
As a taster, here's an example of a dual port synchronous RAM with independent clocks, using Verilog:
reg [W-1:0] mem [0:N-1];
...
always @(posedge ck0) begin
if (we0) begin
mem[a0] = wd0;
rd0 <= wd0;
end else begin
rd0 <= mem[a0];
end
end
always @(posedge ck1) begin
if (we1) begin
mem[a1] = wd1;
rd1 <= wd1;
end else begin
rd1 <= mem[a1];
end
end
For the VHDL version of the example above, much more information, and the code, go to download page. If it's the first time you've downloaded something from our website, we will ask you to register. To read about how we use your details, click here. On the registration form, you will be asked whether you want us to send you further information concerning other Doulos products and services in the subject area concerned.
"Creating FPGA Variants using VHDL"
Alan Fitch, Doulos
This Doulos FPGA Technote compares a number of techniques for creating variants of FPGA designs implemented in VHDL.
VHDL (VHSIC Hardware Description Language) is very popular in the FPGA community as a design entry method. However people sometimes complain that it is hard to make variant designs because VHDL lacks a text pre-processor as is found in C or Verilog.
This Technote looks at techniques for creating variants of designs implemented in VHDL and compares them – including, perhaps surprisingly, the technique of using a text pre-processor! The techniques described have also been tested in a range of tools, and one of the criteria for comparison is portability between different tools.
FPGA Technote Contents include:
A little taster: did you know you can use the GNU C pre-processor on VHDL code?
cpp –P counter.vhd.src counter.vhd
Curious what -P does? Download the full details and code from the download page. If it's the first time you've downloaded something from our website, we will ask you to register. To read about how we use your details, click here. On the registration form, you will be asked whether you want us to send you further information concerning other Doulos products and services in the subject area concerned.
"Asynchronous Signals and Metastability"
Alan Fitch, Doulos
This Doulos FPGA Technote looks at the issue of metastability, and then shows how to use the new metastability calculator in Altera®'s Quartus® II version 9 software.
You can download the Technote and code examples (VHDL and Verilog®).
FPGA Technote Contents include:
Download the full details and code from the download page. If it's the first time you've downloaded something from our website, we will ask you to register. To read about how we use your details, click here. On the registration form, you will be asked whether you want us to send you further information concerning other Doulos products and services in the subject area concerned.
"Implementing multiple configurations on Altera FPGAs"
Bertrand Cuzeau, ALSE
This FPGA Technote by Altera expert Bertrand Cuzeau of ALSE demonstrates how to implement an Altera FPGA-based system that has a factory-default and a user configuration, without even using any external device!
The idea uses the "Remote Update" Megafunction available for most Altera FPGA families.
The Technote contains copyrighted material developed by the Doulos Certified Training Partner - ALSE. Doulos will not accept any claim for damages, howsoever arising, as a result of use of any information provided. This document is not endorsed by Altera.
FPGA Technote Contents include:
Download this Technote from the download page. If it's the first time you've downloaded something from our website, we will ask you to register. To read about how we use your details, click here. On the registration form, you will be asked whether you want us to send you further information concerning other Doulos products and services in the subject area concerned.