Introduction
If you are already an experienced verification engineer familiar with SystemVerilog (or Vera or e or C++) you will probably have little trouble learning the UVM. This article, however, is aimed at a different audience; at those VHDL and Verilog engineers who feel they probably need to do a better job at functional verification, but have not yet found the time or the courage to take a deep dive into SystemVerilog.
In this article we take a look at UVM by considering how you would use UVM to represent ideas familiar to the Verilog or VHDL users, ideas such as design entities, modules, processes, ports, parameters, generics and configuration. Rather than trying to demonstrate all the fancy features of UVM, we will deliberately restrict ourselves to a small, well-behaved subset of the UVM library, which I will informally refer to as Easier UVM.
As a language, SystemVerilog provides the mechanisms you need to create verification components for checking, coverage collection, and stimulus generation, and to modify the behavior of those components as you write specific tests. But SystemVerilog provides more than this, so much more in fact that the learning curve can be daunting for non-specialists. If you are not a verification specialist, what you might need is just enough SystemVerilog to get you going so you can start to benefit from VIP re-use and as a base on which to build as your experience and confidence increase. The aim of Easier UVM is to introduce you to some coding guidelines for UVM that will enable you to do just that.
Easier UVM is not yet another verification methodology. It is UVM. The point is to somewhat restrict the range of features being used in order to make life easier for the novice. In short, where there are multiple ways of doing things we will pick just one, hopefully the cleanest and most well-behaved (though not necessarily your favorite if you happen to be a verification expert already).
If the subject of constrained random coverage-driven verification is unfamiliar to you, you might like to start by reading the UVM Verification Primer.
Open each of the topics below to see a UVM concept presented in terms familiar to the Verilog or VHDL users:
Example
To get you started, we have put together an example written in the Easier UVM coding style that illustrates the points made above and demonstrates some of the new features added in UVM such as the end-of-test objection mechanism, callbacks, and the report catcher. We intend to build an expanded tutorial around this UVM example in due course, but in the meantime, enjoy!
UVM is here at last. This example runs unmodified using simulators from Cadence, Mentor, and Synopsys. Yippee!
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From OVM to UVM: Getting Started with UVM - A First Example
LINKS
Easier UVM Coding Guidelines
Easier UVM - Deeper Explanations
Easier UVM Code Generator
Easier UVM Video Tutorial
Easier UVM Paper and Poster
Easier UVM Examples Ready-to-Run on EDA Playground
Back to the full list of UVM Resources
