At Last, One Functional Verification Methodology for Everyone!
Updated for UVM 1.2
UVM 1.0 was released on 28 Feb 2011 with the explicit endorsement of all the major simulator vendors. Since that time UVM has become the only show in town when it comes to standardized SystemVerilog verification methodologies. UVM has undergone a series of minor releases, which have fixed bugs and introduced new features.
The source code for the original 1.0 release, known as the UVM Base Class Library (BCL), evolved from the UVM Early Adopter release, which in turn was based on OVM version 2.1.1. The most obvious difference between OVM and UVM-EA was that all occurrence of the prefix "ovm_" were quite literally replaced with "uvm_", "OVM_" by "UVM_", "tlm_" by "uvm_tlm_", and so forth. The UVM-EA kit included a script to convert existing OVM source code. UVM-EA added a few new features on top of OVM 2.1.1, which itself added a few new features to OVM 2.0. The most noticeable additions in the 1.0 release were:
- An end-of-test objection mechanism to ease the task of cleaning up at the end of a verification run
- A callback mechanism that provides an alternative to the factory for customizing behavior
- A report catcher to ease the task of customized report handling
- A heartbeat mechanisms to monitor the liveness of verification components.
The UVM 1.0x releases add the following features to the Early Adopter release
- Register layer, based on the Register Abstraction Layer of VMM
- Phasing extensions, meaning a subdivided run phase, user-defined phases, and user-defined relationships between phases
- Sequence mechanism cleaned up, with the old sequence and sequencer macros deprecated
- TLM-2.0 interfaces, based on the SystemC TLM-2.0 standard
- Resource database, improving on the old set_config interface
- End-of-test mechanism cleaned up
- Command line processor, to give access to command line arguments
UVM 1.2 was released in June 2014 and has completed a period of public review. UVM 1.2 is somewhat controversial in that the experts disagree as to whether some of the new features introduced in UVM 1.2 represent a step forward or a step backward. The most conservative advice right now would be to wait-and-see. You do not need to adopt any of the features introduced in UVM-1.2 immediately, and it may be wiser to see how things shake down.
Click here for a Summary of Changes in UVM 1.2
UVM 1.2 includes some bug fixes and some improvements to the documentation, which are welcome changes, of course. There are two specific features of UVM 1.2 that you might like to know about right away. The starting_phase variable has been deprecated and replaced with two methods set_starting_phase and get_starting_phase, so you might like to start using these methods. Also, there is a new method uvm_objection::set_propagate_mode that can be used to switch off the hierarchical propagation of objections and thus speed up simulation in some circumstances. (The propagation of objections is usually redundant anyway.)
